This trivial design will work regardless, but right now I'm more concerned with figuring out how the synthesis tools work in as much detail as possible and tinkering with a simple design to see how the output changes. Should I be trying to use the output of the 'slow clock' module directly or should I run the master clock to the led counter module and then gate it with the slow clock? Should I set the clock frequency at all in the HDL or should I leave that out and only set it in synthesis options? Or do I need to set it in the HDL and manually match it up with synthesis options?įor things like clocks driving counters that then output a 'clock', what's the proper way to set constraints? Do I configure it as a false path, a multi cycle path, or what?

I can read the manual and set constraints here but it's not very clear what the best practices are for clock constraints. Now the important part: when I synthesize this with Synplify pro it correctly detects the primary clock but then detects the 'slow clock' module as a clock and gets the timing wrong. That output then goes to a blinky led module that counts up infinitely and reveals the state of the 8 bit counter on some LEDs. That clock then connects to a module that increments a counter and flips an output register every 100000 cycles. What I did was instantiate the internal oscillator block (OSCH) for the MachXO3 and defparam'd the frequency to the minimum of 2.08 in Verilog. I'm fiddling with the options using a trivial blinky led design using two counters and 8 LEDs.

Right now I'm trying to get a handle on the best way to set clock speed and timing constraints, specifically using Synplify Pro.

Synplify pro prevent clock inference